Because digital signal processing circuit designers continue to use the same hardware building blocks, such as the (static) random access memory (RAM), MOSFET-configured, data bit cell diagrammatically illustrated in FIG. 1, to implement a variety of product designs, enhancements in system performance have been essentially governed by improvements in line widths and manufacturing processes of integrated circuit components that enable data processing architectures to operate at faster speeds and store more data in smaller volumes of semiconductor material.
Although the memory cell of FIG. 1 is shown as a metal oxide semiconductor (MOS) transistor-configured cell, it should be observed that the cell may be implemented using other components, such as but not limited to bipolar devices, biCMOS devices, and the like. In the example shown in FIG. 1, the MOSFET memory cell, shown at 10, is comprised of a pair of cross-connected inverters 11 and 12 that are coupled to power supply rails V.sub.DD, V.sub.GG and ground (GND), and having complementary data bit nodes D and D BAR that store complementary bit logic levels representative of the data bit stored in the cell. MOS transistors T1 and T2 are the respective drive and load transistors of inverter 11, while MOS transistors T3 and T4 are the respective drive and load transistors of the other inverter 12. Within a memory comprised of two-dimensional array of such cells, the X and Y locations, and therefore the address, of the memory cell are defined by an X node 21, that is coupled to the X address node of other memory cells of the same row of the memory array, and a Y node 22, that is coupled to the Y address node of other memory cells of the same column of the memory array.
The X node 21 is coupled to the gates of row address transistors T5 and T6, which have their source-drain paths coupled between respective data nodes D and D BAR and complementary Data and Data BAR lines 31 and 32. The Data and Data BAR lines 31 and 32 are coupled to other memory cells of the same Y column of the memory array. The Y node 22 is coupled the gates of column address transistors T7 and T8, which have their source-drain paths respectively coupled in circuit with the source-drain path of a data input (or write) transistor T9 and a data output (or read) transistor T10.
To store or write data into the memory cell, the source-drain path of data input transistor T9 is coupled to a data input (Data in) node 41 and its gate is coupled to receive a write control signal W. To read data from the memory cell, the source-drain path of data output transistor T10 is coupled to a data output (Data Bar out) node 42 and its gate is coupled to receive a read control signal R. When writing or reading data, the cell is addressed by applying a prescribed logic level (e.g., `1`) to the respective X and Y,address nodes 21 and 22, so as to turn on transistors T5, T6, T7 and T8. With transistors T5 and T7 turned on, the data node D is coupled to data input transistor T9, while the complementary data node D BAR is coupled to the data output transistor T10.
In order to write data into the memory cell 10, the write control input W to the gate of data input transistor T9 is asserted at a prescribed logical state (e.g., `1`), while the read control input R to the gate of data output transistor T10 is asserted at a complementary logical state (e.g., `0`), thereby turning on transistor T9 and holding transistor T10 off during a respective `write cycle`. If the bit value applied to the Data in node 41 is a `1`, the resulting `1` at data node D turns on transistor T3, thereby coupling the complementary data node D BAR to GND or `0`. Namely, the data line 31 is at the input data value `1`, while the complementary data line D BAR 32 is at a logical `0` value. On the other hand, if the bit value applied to the Data in node 41 is a `0`, the resulting `01` at data node D turns transistor T3 off, so that complementary data node D BAR is at a logical `1`. In this case, the data line 31 is at the input data value `0`, while the complementary data line D BAR 32 is at a logical `1` value.
To read data from the memory cell 10, the read control input R to the gate of data input transistor T10 is asserted at a prescribed logical state (e.g., `1`), while the write control input W to the gate of data input transistor T9 is asserted at a prescribed complementary logical state (e.g., `0`), thereby turning on transistor T10 and holding transistor T9 off. Since each of transistors T5, T6, T7 and T8 is turned on, then during this `read cycle`, whatever bit value is stored in the memory cell 10 will be coupled to Data line 31, while its complement will be coupled to Data BAR line 32.
In addition to being selectively addressable so as to allow data to be written into or read out, the memory cell may be configured as an associative or content addressable memory (CAM) cell, that enables its stored data bit to be compared or associated with a prescribed `comparison` bit value. For this purpose, the memory cell of FIG. 1 may be augmented as diagrammatically illustrated in FIG. 2 to include a bit value comparator or `match` circuit 50, that is coupled to the data nodes and data lines of the cell.
A typical comparator employed for this purpose may comprise an exclusive NOR circuit having first and second pairs of sense transistors T11-T13 and T12-T14, with their drain-source paths coupled in circuit between a reference potential node (e.g., GND) and a compare or `MATCH` line 51, that is wire-AND coupled to other cells of the same word's key field. The gate of transistor T11 is coupled to the data line side of the source-drain path of transistor T5, while the `sense` input or gate of transistor T13 is coupled to the data node D of the memory cell 10. On the complementary side, the gate of transistor T12 is coupled to the Data line BAR side of the source-drain path of transistor T6, while the `sense` gate of transistor T14 is coupled to the data node D BAR of memory cell 10.
This auxiliary comparator circuitry allows the content addressable memory cell configuration of FIG. 2 to conduct an associative or comparison operation during a match cycle that is separate from the write and read cycles in the manner described above with reference to FIG. 1. In particular, during a comparison cycle, the match line 51 is charged to a prescribed (high) level. Since the purpose of an associative operation is to `assert data` and `read address information` , the X address node 21 is asserted low, so as keep transistors T5 and T6 turned off, thereby isolating the memory cell and preventing its contents from being affected by the comparison operation being performed. Also, the write W and read R control inputs are controllably multiplexed, so as to couple comparison data to the data lines through the input transistor T9 and the data output transistor T10.
Namely, the data bit and its complement with which the bit stored in the memory cell is to be compared are selectively applied to the Data BAR line 32 and its complement Data line 31, by turning on the transistors T9 and T10, the source-drain paths of which are coupled to the gates of transistors T12 and T11. Since the `sense` gate of transistor T13 is coupled to the data node D and the `sense` gate of transistor T14 is coupled to the data node D BAR of the memory cell 10, a `match` can occur only if the stored bit and the comparison bit have the same value.
Because both the write or data input transistor T9 and the read or data output transistor T10 are employed during a comparison cycle in the conventional CAM of FIG. 2, not only are the read and compare operations performed mutually exclusively from a memory cell write cycle (which must occur for proper operation of the memory cell), but they are performed mutually exclusively of each other (which is not absolutely essential for memory cell operation). This use of separate cycles for read and compare modes constitutes an unnecessary impairment to the performance potential of the memory cell.